
`include "defines.v"

module pc (
    input  wire              clk,
    input  wire              rst,
    
    input  wire [`BUS_WIDTH] offset,
    output reg  [`BUS_WIDTH] inst_addr
);


    parameter PC_START_RESET = `PC_START - 64'b100;

    always @(posedge clk) begin
        if (rst) begin
            inst_addr <= PC_START_RESET;
        end
        else begin
            inst_addr <= inst_addr + offset;
        end
    end


endmodule
